• Rackmount chassis with minimum 400W power supply & motherboard supporting 7th Generation Intel Core-i7 central processing units, 4x PCI-e Expansion slots, 1x network interface supporting real-time UDP, 1x Gigabit Ethernet port, 1x RS232 COM port, 1x USB port, 1x VGA display port, 1x SSD of at least 64 GB, and minimum 4096 MB of RAM.
• Configurable FPGA-based I/O module with Xilinx Artix 7 FPGA
• I/O (input/output) module providing minimum of 4x differential simultaneous sampling 12-bit analog inputs, (voltage range: +/- 5V), 8x simultaneous sampling 12-bit analog outputs (voltage range: +/- 5V), and 16x configurable digital TTL I/O lines.
• I/O providing module minimum of 32 x TTL I/O lines with ESD and overvoltage protection.
• I/O providing IRIG and GPS 1PPS precision time I/O accurate to at least UTC ±50ns
• MATLAB Mathworks R2018a Simulink HDL Coder integration blockset for Xilinx Artix 7 FPGA with reference design.
• MATLAB Mathworks R2018a Simulink I/O driver blockset
• MATLAB Mathworks R2018a Simulink SPI I/O configuration blockset
• MATLAB Mathworks R2018a Simulink PWM I/O configuration blockset
• MATLAB Mathworks R2018a Simulink precision time I/O configuration blockset

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